Application-specific array processors for binary prefix sum computation

The main contribution of this work is to propose two application-specific bus architectures for computing the p r e f i sums of a binary sequence. Our architectures feature the following characteristics: (1) all broadcasts occur on buses of length I5 or 63; ( 2 ) we use a new technique t h a ~ we call shift switching which allows switches to cyclically permute an incoming signul, dramatically improving the performance of the reconfigurable bus system. As it turns out, our special-purpose architectures improve the performance of the best algorithm known to date by a significant factor. Specifically, our solutions require no adders, are faster, and use less VLSI area than the architectures of the state of the art.